April 30, 2011 - (Memory and Data Parallelism on Multi- and Manycore Platforms)
"Memory and Data Parallelism on Multi- and Manycore Platforms"
at the PPAM 2011 (http://www.ppam.pl/)
The peak performance of modern microprocessors is still doubling every 18
months as it has been the case for years according to Moore's Law. However,
this improvement is now achieved via more parallelism on all levels, as
reflected by the strong trend towards multi- and manycore architectures, but
also towards more data parallelism on the instruction level. The latter
becomes apparent in the increasing size of SIMD units and vector registers,
and can also be observed in GPGPUs and other accelerator hardware. In addition,
neither memory latency nor memory bandwidth have been able to keep up with the
exponential growth in computational speed, nor are they likely to do so in the
imminent future. As a consequence the already existing gap between processor
and memory performance is steadily growing.
Exploiting the performance available on modern computing platforms has
therefore become a difficult job. Multi-level caches that can be dedicated to
or are shared between the processor cores, as well as NUMA-style memory access
have to be considered. Algorithms and implementations have to take care of data
parallelism. And critical parts of the code, especially those operating on
simple regular data structures (arrays, etc.), might have to be offloaded to
Hence, in our workshop, we want to address all kinds of memory- and
data-parallelism-related issues for high performance computing on multi- and
manycore-based architectures. Areas of interest for workshop submissions
therefore include, but are not limited to:
* Hardware-aware, compute- and memory-intensive simulations of real-world
problems from electrical, mechanical, civil, or medical engineering
requiring parallelisation on multicore platforms.
* Architecture-aware, and particularly multi- and manycore-aware approaches
in both implementation and algorithm design, including scalability studies.
* Tools for performance and cache behavior analysis (including cache
simulation) for parallel systems with multicore processors, as well as
respective cache performance studies.
* Parallelisation with appropriate programming models and tool support for
multicore and hybrid platforms.
* Performance studies and first experiences on the latest multi- or
many-core processors, as well as on accelerator hardware.
* Ease-of-use for accelerator-based platforms, such as GPGPUs or Many
Integrated Core architectures.
* Impact of data parallelism through use of sophisticated vector units.
Paper Submission and Publication:
All rules of paper submission of the PPAM conference apply. In particular:
* Papers will be refereed and accepted on the basis of their scientific
merit and relevance to the Workshop topics.
* Papers presented at the Workshop will be included into the conference
proceedings and published after the conference by Springer in the LNCS
* Before the Workshop, abstracts of accepted papers will be posted on its
Authors should submit their papers via the PPAM online submission system
at Easychair, see http://www.ppam.pl/submission, by April 30, 2011.
Papers are not to exceed 10 pages (LNCS style).
Submission of Papers: April 30, 2011
Notification of Acceptance: June 15, 2011
Conference: September 11-14, 2011
Camera-Ready Papers: Oct 31, 2011
Michael Bader, Universität Stuttgart, Germany
Carsten Trinitis, Technische Universität München, Germany
Josef Weidendorfer, Technische Universität München, Germany